1. Field of the Invention
This invention relates to the automatic synthesis of a segmented channel architecture for row-based field programmable gate arrays (FPGAs) and more particularly relates to the use of a simulated annealing based channel architecture synthesis algorithm which has been developed to achieve maximum routability and performance of a channel architecture for various FPGA designs.
2. Description of the Prior Art
Field Programmable Gate Arrays (FPGAs) combine the flexibility of mask programmable gate arrays with the convenience of field programmability. We consider row-based architecture for FPGAs as shown in FIG. 1. Rows of logic modules are separated by channels which are used for the routing of the nets. Only 2 rows (row1 and row2) of logic modules, with each row having three logic modules (LM1-LM6), are shown in FIG. 1. The two rows are shown separated by a single channel having three horizontal tracks T1-T3. However, typical FPGAs may have 20 rows of logic modules with 44 logic modules in each row. Each logic module can implement various types of logic functions and each logic module can be connected to any other logic module through pins on the logic modules as is well known. The routing resources are limited as there are a fixed number of horizontal routing tracks hardwired in each channel. The routing tracks are also segmented. For example, FIG. 1 has 3 tracks per channel of which the topmost track T1 is divided into two segments sa and sb separated by a horizontal antifuse HA1. In the unprogrammed state the antifuse HA1 offers a very high resistance, and hence, there is no electrical connection between the segments sa and sb. A low resistance electrical connection between the segments sa and sb can be established by programming the antifuse HA1. Dedicated vertical lines VA through each input and output pin of a logic module connect the pins to the routing tracks T1-T3. Vertical feedthroughs pass through the modules, serving as links between channels. There is a cross antifuse CA located at the crossing of each horizontal and vertical segment. Programming these antifuses produces a bi-directional connection between the horizontal and vertical segments. Let us again consider FIG. 1. The net names are shown at its constituent pins' locations. There are three available choices for routing net 1-segments sa and sb (requires programming of an antifuse HA1 between segments sa and sb, and two cross antifuses CA1 and CA2); segment sc (requires programming two cross antifuses CA3 and CA4); or segments sd and se (requires programming of a horizontal antifuse HA2 between segments sc and sd, and two cross antifuses CA5 and CA6). Once net 1 is assigned to one or more segments, those segment(s) are unavailable for further usage by any other net.
The routing resources are fixed, and hence, the channel segmentation scheme has an enormous effect on performance and routability of a channel. Efficient usage of horizontal antifuses is required for routability and for meeting the critical path delay (performance) requirements. Intuitively, a strong correlation between the segment length and the net length distributions within a channel is very desirable. However, the mere existence of a unique segment of acceptable length for every net in a channel does not guarantee 100% routability. This is due to the fact that an additional factor, the location of a segment with respect to a net span in a channel is also important in determining whether that segment can be used for routing that net. It is imperative, therefore, to consider the spatial distributions for segments and nets when developing a particular channel architecture. Once a channel architecture is developed for a particular FPGA net design, it may be desirable that the particular channel architecture also be useful for various other net designs. This is especially so, due to the reprogrammable nature of current FPGA's. Prior art FPGA channel architecture was developed with a sort of hit or miss approach with a desire toward selecting a random distribution of channel segmentation.
It is therefore a general object of the present invention to develope a channel segmentation architecture for row-based FPGA's which provides for good routability and performance over a large set of FPGA net designs.
It is further object of the present invention to develope a channel segmentation architecture for row-based FPGA's which maximizes the correlation between the spatial distribution of segments of the channel architecture and the nets over a large set of FPGA net designs.
It is a further object of the present invention to route the nets of a particular FPGA design with maximum performance and routability, once a particular channel segmentation architecture has been developed.
These and other objects of the invention will become apparent to those of ordinary skill in the art having reference to the following specification, in conjunction with the drawings.